The present invention relates to a semiconductor memory device; more particularly, to an internal voltage generator for use in the semiconductor memory device.
A dynamic random access memory (DRAM), which is a kind of semiconductor memory device, inputs and outputs data through following processes. If a row address strobe command is inputted to the DRAM, a word line corresponding to an input address is activated. Data stored in unit cells corresponding to the word line are transmitted to bit line pairs. The transmitted data is sensed and amplified by bit line sense amplifiers. Thereafter, when a column address strobe command is inputted to the DRAM, a column selecting signal is generated according to an input address and one bit line pair is selected by the column selecting signal. A data amplified in the selected bit line pair is outputted or replaced with an external input data according to a write enable command. And then, the bit line pair is precharged and initialized for a subsequent read or write operation.
During the above-mentioned processes, a period from an input timing of the row address strobe command to a beginning of a precharge operation is called a row active time tRAS. A minimum row active time tRASmin is a minimum time required to perform a read or write operation after the row address strobe command is input. That is, the minimum row active time tRASmin is a minimum time for bit line sense amplifiers to sense and amplify data stored in unit cells corresponding to a selected word line. The minimum row active time tRASmin should be guaranteed for the data not to be lost.
The bit line sense amplifiers amplify the data based on a core voltage VCORE. Thus a DRAM should prevent a level of core voltage VCORE from decreasing or fluctuating. However, after the minimum row active time tRASmin passes from the input timing of the row address strobe command, the core voltage VCORE is less used in the DRAM until the read or write operation is performed. Nevertheless, the DRAM operates active drivers supplying the core voltage VCORE during above-mentioned period in the same manner as other periods. As a result, current consumption increases.
FIG. 1 is a block diagram showing a conventional internal voltage generator. The internal voltage generator includes an initial voltage generator 10 for determining an initial condition of a core voltage VCORE, a standby mode voltage generator 11 for generating the core voltage VCORE, six active mode voltage generators 12 to 17 for generating the core voltage VCORE during an active operation and a controller 18 for controlling a half of active mode voltage generators 12 to 14.
The controller 18 controls the active mode voltage generators 12 to 14 in response to a write/read signal W/RSIG and an internal voltage active signal VINTACT. The internal voltage active signal VINTACT has been activated from an input timing of a row address strobe command until a minimum row active time tRASmin passes. The controller 18 includes a first NOR gate NOR1 and a first inverter INV1. The first NOR gate NOR1 receives the write/read signal W/RSIG and the internal voltage active signal VINTACT. The first inverter INV1 inverts an output of the first NOR gate NOR1 to output control signals.
Because the core voltage VCORE is more used during the active operation including read or write operation, the plurality of the active mode voltage generators 12 to 17 is additionally used during the active operation. The standby mode voltage generator 11 generates the core voltage VCORE during both the active operation and a precharge operation. All of the standby and active mode voltage generators 11 to 17 are supplied with an external reference voltage VREFC.
Three active mode voltage generators 15 to 17 are controlled by a boosted voltage active signal VPPACT. The boosted voltage active signal VPPACT is activated when a word line is selected by a row address and inactivated at the precharge operation. The boosted voltage active signal VPPACT is for supplying a boosted voltage to the word line.
FIG. 2 is a signal timing diagram showing an operation of the internal voltage generator described in FIG. 1.
Under the condition that the reference voltage VREFC is supplied to the standby and active mode voltage generators 11 to 17, the internal voltage active signal VINTACT and the boosted voltage active signal VPPACT are activated as a high level at an initial active operation. And the write/read signal W/RSIG has a low logic level until the write or read operation begin.
Accordingly, the controller 18 outputs the control signals as a high level and operates the active mode voltage generators 12 to 14. The active mode voltage generators 15 to 17 are enabled by the boosted voltage active signal VPPACT. All of the active mode voltage generators 12 to 17 operate at the initial active operation.
After a minimum row active time tRASmin passes, the internal voltage active signal VINTACT becomes in a low logic level. And the active mode voltage generators 12 to 14 stop operating for a period A described in FIG. 2. The active mode voltage generators 15 to 17 continue to operate because the boosted voltage active signal VPPACT maintains a high logic level.
Thereafter, when the write/read signal W/RSIG is activated, the controller 18 outputs the control signal having a high logic level. All of the active mode voltage generators 12 to 17 continue to operate until the precharge operation begins. When the boosted voltage active signal VPPACT and the write/read signal W/RSIG are inactivated in response to a precharge signal activated at the precharge operation, all of the active mode voltage generators 12 to 17 stop operating.
Accordingly, the internal voltage generator generates the core voltage VCORE only in response to the boosted voltage active signal VPPACT during the period A. The internal voltage generator enables the active mode voltage generators 15 to 17 without respect to the level of core voltage VCORE, thereby to generate a constant voltage. However, when the level of core voltage VCORE is higher than the reference voltage VREFC, it is efficient to enable less active mode voltage generators to decrease current consumption. The conventional internal voltage generator cannot appropriately deal with the variation of the core voltage VCORE.